From Sand to Silicon: The Incredible Journey of Processors

Sand / Ingot

Silicon sand is the second most abundant element in the earth's crust. Ordinary sand contains high silicon content. This means that silicon, which is the starting material for computer chips, is a semiconductor—one that can easily be converted into a perfect conductor or electrical insulator by adding small amounts of foreign material. Molten Silicon - Scale: Wafer level (~ 300mm). Silicon must be purified for use in computer chips, so there must be fewer than one foreign atom per billion. An ingot is drawn from the molten state to form a single, uninterrupted and unbroken crystal lattice in the shape of a cylinder. Monocrystalline Silicon Ingot - Scale: Wafer level (~ 300mm) The ingot has a diameter of 300 mm and weighs approximately 100 kg.

Ingot / Wafer

Ingot Slicing - Scale: Wafer level (~ 300mm) The ingot is cut into individual silicon disks called wafers. Each wafer has a diameter of 300 mm and approximately 1 mm thickness. Wafer - Scale (~ 300mm / 12 inches) Wafers are polished until they reach flawless, smooth surfaces. Intel purchases manufacturing-ready wafers from its suppliers. Wafer sizes have increased over time and the cost per chip has decreased. When Intel began making chips, wafers had a diameter of only 50 mm. Today they reach 300 mm in diameter and are planned to increase to 450 mm.  

Photolithography

Photoresist Application - Scale: Wafer level (~ 300mm) Photolithography is the process by which a specific pattern is printed on a wafer. It begins with the application of a liquid known as photoresist, which is sprayed and evenly distributed on the wafer. Its name comes from the fact that it is sensitive to certain light frequencies ("photo") and subsequently resists certain chemicals that will be used to remove portions of a layer material ("resist"). Exposure - Scale: Wafer level (~ 300mm) The photoresist is hardened and some parts are dissolved by exposure to ultraviolet (UV) light. The exposure is performed using masks that act like templates, so only a certain photoresist pattern becomes soluble. The mask has a model image that should rest on the wafer; it is optically reduced with a lens and the exposure tool steps and repeats across the wafer to create the same image many times. Resist Development - Scale: Wafer level (~300mm) The soluble photoresist is removed through a chemical process, leaving behind a pattern defined by the mask.

Ion Implantation

Ion Implantation - Scale: Wafer level (~ 300mm) The surface of the patterned photoresist wafer is buried below the surface and exposed areas not covered by photoresist are bombarded with an ion beam (positively or negatively charged atoms). This process is called doping because impure materials enter the silicon. This changes silicon's conductive properties in selected locations (making it conductive or insulating depending on the type of ion used). The graphs below show the creation of wells, which are the regions where transistors will form. Photoresist Removal - Scale: Wafer level (~ 300mm) After ion implantation, the photoresist is removed and the resulting wafer has a pattern consisting of doping regions where transistors will be built. Transistor Formation Begins - Scale: Transistor level (~ 50-200nm) Here we are zooming in on a small wafer area where a single transistor will be formed. The green region represents doped silicon. Today's wafers can have hundreds of billions of regions to house transistors.   Etching Etch - Scale: Transistor level (~ 50-200 nm) In order to create a fin for a three-gate transistor, a material pattern with a hard mask (blue) is applied using photolithography. A chemical is then applied to remove unwanted silicon, leaving a fin with a hard mask layer on top. Photoresist Removal - Scale: Transistor level (~ 50-200nm) The hard mask is chemically removed, leaving a long, thin silicon fin that will contain a transistor channel.

Temporary Gate Formation

Dielectric Silicon Dioxide Gate - Scale: Transistor level (~ 50-200 nm) Using a photolithography step, transistor sections are covered with photoresist and a thin silicon dioxide layer (red) is created by placing it in an oxygen-filled tube furnace. This creates a temporary dielectric gate. Polysilicon Gate Electrode - Scale: Transistor level (~ 50-200nm) Again using a photolithography step, a temporary polycrystalline silicon layer (yellow) is created. This becomes a temporary gate electrode. Insulator Scale: Transistor level (~ 50-200 nm) In another oxidation step, a silicon dioxide layer (red / transparent layer) is created over the entire wafer to isolate this transistor from other elements.

"Final Gate" High-k / Metal Gate Formation

Temporary Gate Removal - Scale: Transistor level (~ 50-200nm) The temporary gate electrode and gate dielectric are removed using a masking step. The actual gate is now being created; because the first gate has been removed, this process is known as "final gate". High-k Dielectric - Scale: Transistor level (~ 50-200nm) Application: In a process called "atomic layer deposition", individual molecular layers are applied to the wafer surface. The yellow layers shown in the graph on the other page represent two of these. The high "-k" material is removed from unwanted areas, such as areas above transparent silicon dioxide, using a photolithography step. Metal Gate - Scale: Transistor level (~ 50-200 nm) A metal gate electrode (blue) is created on the wafer and removed from areas other than where the gate electrode is desired, using a lithography step. This combination of metal gate and high-k material (thin yellow layer) allows the transistor to perform much better than would be possible with a conventional silicon dioxide / polysilicon gate and reduces leakage.

Metal Deposition

Finished Transistor - Scale: Transistor level (~ 50-200nm) This transistor is nearly complete; three holes have been etched in the isolation layer (shown in red) above the transistor. These three holes will be filled with copper or other materials to create connections with the transistors. Electroplating - Scale: Transistor level (~ 50-200nm) At this stage, the wafers are placed in a copper sulfate solution. Copper ions are transferred to the transistor through a process called electroplating. Copper ions pass from the positive terminal (anode) to the negative terminal (cathode) represented by the wafer. After Electroplating - Scale: Transistor level (~ 50-200 nm) Copper ions deposit on the surface as a thin copper layer.  

Metal Layers

Polishing - Scale: Transistor level (~ 50-200nm) Excess material is mechanically polished to reveal the specific pattern of copper. Metal Layers - Scale: Transistor level (6 combined transistors ~ 500nm) Multiple metal layers are created to connect all transistors on the chip in a specific configuration (think of them as miniature wires or cables). The architecture and design teams determine how these connections will be "wired", enhancing the functionality of the processors in question (e.g., 2nd Generation Intel® Core ™ i5 Processor). Although computer chips appear extremely flat, they can have more than 30 layers to create complex circuits. A magnified view of the chip would show a tangled network of circuit lines and transistors, resembling a futuristic, multi-layered highway system. After all connection layers have been created, a series of solder bumps is placed on each die. These are the electrical connections through which the chip will communicate with the outside world in the package into which it is later installed (these are not shown in the graphics). When wafer processing is complete, the wafer is transferred from the fab to the assembly / test facility. There, individual dies still on the wafer are tested, then separated, and those that pass are packaged. Finally, a comprehensive test of the packaged part is performed before the finished product is shipped.

Wafer Sorting / Singulation

Wafer Sorting - Scale: Die level (~ 10mm) This part of a finished wafer is undergoing testing. A test device moves across the wafer, making contact at specific points on the wafer, and an electrical test is performed. Test patterns are matched with each die, the response from the die is monitored and compared to the "correct answer". Wafer Slicing - Scale: Wafer level (~ 300mm) The wafer is cut into pieces (called dies). In the wafer shown in the graphic, Intel processors code-named Ivy Bridge are found. Die Selection for Packaging - Scale: Wafer level (~ 300mm) Dies that respond with the correct answer to test dies will be packaged. Packaging Individual Die - Scale: Die level (~ 10mm) These are individual dies that were cut in the previous step (singulation). The die shown in the graphs on the next page is Intel's first 22nm microprocessor, called Ivy Bridge. Packaging - Scale: Package level (~ 20mm) The package substrate, die and heat spreader are assembled to form a finished processor. The green substrate layer creates the electrical and mechanical interface for the processor to interact with the rest of the PC system. The silver heat spreader is a thermal interface that aids in heat dissipation. Processor - Scale: Package level (~ 20mm) The finished processor, the example here is Ivy Bridge. A microprocessor has been called the most complex manufactured product ever made by humans. In fact, the process takes hundreds of steps in the world's cleanest environment (a microprocessor factory)—this article has attempted to explain only the most important steps with graphics.

Grade Testing / Finished Processor

Grade Testing - Scale: Package level (~ 20mm) During this final test, the processor is tested intensively for functionality, performance and power. Binning - Scale: Package level (~ 20mm) Based on grade test results, processors with equal capacity are grouped together on trays, ready to be shipped to customers. Retail Packaging - Scale: Package level (~ 20mm) The now-finished and tested processors are sent in bulk on these trays to PC system manufacturers or in boxes to retail stores.

References • https://newsroom.intel.com/press-kits/from-sand-to-silicon-the-making-of-a-chip/ • https://newsroom.intel.com/press-kits/intel-22nm-3-d-tri-gate-transistor-technology/ • Weik, Martin H. (1961). "A Third Survey of Domestic Electronic Digital Computing Systems". Ballistic Research Laboratory. • Stanford University. "The Modern History of Computing". The Stanford Encyclopedia of Philosophy. Retrieved September 25, 2015. Graphics • Copyright © Intel Corporation. All rights reserved. • Copyright © Intel Corporation. All rights reserved.